image processing reference design using Xinlinx Zinq US FPGA
- C++ 56.6%
- C 31.8%
- Python 5.4%
- Tcl 5.3%
- Shell 0.4%
- Other 0.5%
| Filename | Latest commit message | Latest commit date |
|---|---|---|
| mega_dualpeak_v3 | ||
| mega_sw | ||
| .gitignore | ||
| 2026.01.21.Mega_dualpeak_110MHz_v4.6.6.FWID-1221.frm | ||
| FPGA_REBUILD_GUIDE.md | ||
| fpp_core_integration_assessment.org | ||
| README.md | ||
SPINOS - FPGA Projects Repository
This repository contains FPGA design projects for the SPINOS platform, including Vivado designs for Xilinx Zynq UltraScale+ devices and associated software tools.
Repository Structure
spinos/
├── mega_dualpeak_v3/ # Vivado FPGA design for Mega DualPeak V3
├── mega_sw/ # Software development tools and Linux support
└── *.frm # Firmware files (e.g., firmware updates)
mega_dualpeak_v3 - FPGA Design
FPGA design for Mega DualPeak V3 project based on Xilinx Zynq UltraScale+ ZU4CG.
Requirements
- Xilinx Vivado 2021.2
- Target device: xczu4cg-fbvb900-1-e
Building the FPGA Design
cd mega_dualpeak_v3
source ~/opt/Xilinx/Vivado/2021.2/settings64.sh
vivado -mode batch -source mega_dualpeak_v3_vivado_project.tcl
Opening in Vivado GUI
vivado project_mega_dualpeak_v3/mega_dualpeak_v3.xpr
Project Contents
- Block Design:
bd/mega_dualpeak_v3-zusys.tcl- Zynq UltraScale+ system block design - Constraints:
sdc/- XDC constraint files (pins, debug, timing) - IP Definitions:
ipdefs/- Custom and third-party IPs including:- axi_lux2810 (RX channel interface)
- axis_peak (peak detection pipeline)
- eth_10g (10 Gigabit Ethernet MAC)
- And various AXI stream processing blocks
mega_sw - Software Tools
Software development environment for the Zynq platform including:
- cam_control.mega_v3/: Camera control applications
- devicetree/: Device tree sources
- linux/: Linux kernel configuration and patches
- petalnx/: PetaLinux project files
- u-boot/: U-Boot bootloader
- scripts/: Build and deployment scripts
- sd_disk/: SD card disk image utilities
Prerequisites
- Linux 64-bit OS (Ubuntu 20.04 LTS recommended)
- Xilinx Vivado 2021.2 tools installed
- Install Xilinx tools in your home directory (e.g.,
~/opt/Xilinx) to avoid permission issues
Build Instructions
Refer to the README.md files in each subdirectory for specific build instructions.
Notes
mega_10gbeth_ptp Design Note
Some designs in this repository are based on Xilinx 10G Ethernet PTP reference designs. These may have:
- Different QSPI partition layouts
- Custom Xilinx axienet driver with PTP support (megalodon_ptp_defconfig)
Repository Information
- Git URL: [email protected]:Pcsf/spinos.git